As circuit geometries become increasingly smaller and clock rates become increasingly higher, power dissipation in digital circuits is a parameter that must be kept under control. Higher clock rates, higher leakage currents associated with smaller geometries, and higher circuit densities all drive toward higher power densities, which must be addressed using power dissipation methods, such as larger heat sinks, to avoid degradation in reliability. A further challenge is proliferation of portable, battery powered devices, which are evolving toward reduced size and weight, and have limited available power and limited room for heat sinks. Therefore, techniques to reduce power consumption in digital circuits are becoming increasingly important.
Additionally, as application software becomes more sophisticated and complex, demand for larger memory sizes is increasing. As a result, solid state memory circuits are becoming larger and may occupy a large portion of a digital circuit design. Larger memory sizes require more decoding circuitry to provide decoded memory access signals to individual memory blocks. As such, higher clock rates may place significant timing demands on decoding circuitry, which may become increasingly complex with larger memory sizes. The timing demands may place limitations on maximum allowable timing delays in the decoding circuitry for proper memory circuit operation. Thus, there is a need to reduce power consumption in solid state memory circuits and to reduce timing delays in the decoding circuitry associated with solid state memory circuits.